FPGA Embedded Design/ Part 1 – Verilog

About Course

Learn FPGA Embedded Design with Verilog for free! This comprehensive course covers the essential concepts of FPGA design using Verilog, one of the most widely used Hardware Description Languages. You’ll gain a deep understanding of concurrent programming in Verilog and master the art of designing digital systems.

This course provides a strong foundation in FPGA design, including hardware description languages, digital logic, and system design. You’ll learn how to create and test your own Verilog designs, building a solid foundation in FPGA technology.

This course is ideal for anyone interested in learning about FPGAs, embedded systems, or digital design. Start your journey into the exciting world of FPGA Embedded Design today! This course is completely free and available on Theetay from platforms like Udemy, Udacity, Coursera, MasterClass, NearPeer, and more.

Design hardware behavior with the Verilog Hardware Description Language
Simulate Verilog Modules.
The curriculum will take you by the hand through learning Verilog.
In the series, you'll learn how to simulate your designs, how to make them real in an FPGA, and finally how to design and use your own Soft Processor
This first course is about the Verilog Hardware Description Language.
This is NOT a System Verilog course. However, learning Verilog is a starting point if you want to learn System Verilog (Similar to learning C prior to C++).

Course Content

Introduction

A Message from the Professor
Course Structure

03:26
Instructor Introduction

00:40
Motivation Hardware Design

03:00
Motivation CPU Design

01:27
Course Material Download Link

00:00

Hardware Description Languages

[Optional] Refresher on Digital Circuit Design

Digital Circuit Design

02:02
Combinational Logic – Muxes and Demuxes

04:12
Combinational Logic – Logic with Multiplexers

02:54
Combinational Logic – Logic with Demultiplexers

02:01
Combinational Logic – Inside Multiplexers and Demultiplexers

02:56
Arithmetic with Gates

05:43
Adders with Gates

04:03
Sequential Logic

05:52
Tri-State Buffers

05:04

The Verilog Hardware Description Language

Software Tutorial

Quick Overview of EDA Playground

Quick Overview of Modelsim

Coding Elements of Verilog

Wires and Registers

02:16
Number Representation Logic Values

03:51
Number Representation Integers

03:25
Logic Gates

01:07
Higher-Level statements

00:54
Data Assignments

01:47
Multiplexers and Demultiplexers

00:19
Tri-State Buffers in Veriog

03:41
Sequential Logic

07:21
Blocking vs Nonblocking Assignments

03:18
Assignment example in EDA Playground

02:44
Blocking Results

03:14
Nonblocking Results

03:21
Nonintuitive Results

01:00

A Combinational System Example

A Sequential System Example

Wrap Up

Add this certificate to your resume to demonstrate your skills & increase your chances of getting noticed.

Student Ratings & Reviews

5.0

Total 1 Rating

1 Rating

0 Rating

Ahmad Mushtaq

12 months ago

I started this course while studying DLD course in my university. It really helped me through the Verilog programming and Eduardo is really good at explaining the HDL stuff. Much recommended to DLD or DSD students

About Course

What Will You Learn?

Course Content

Introduction

A Message from the Professor

Course Structure

Instructor Introduction

Motivation Hardware Design

Motivation CPU Design

Course Material Download Link

Hardware Description Languages

What exactly is a Hardware Description Language

Concurrent Design

Verilog and VHDL

Other HDLs

[Optional] Refresher on Digital Circuit Design

Digital Circuit Design

Combinational Logic – Muxes and Demuxes

Combinational Logic – Logic with Multiplexers

Combinational Logic – Logic with Demultiplexers

Combinational Logic – Inside Multiplexers and Demultiplexers

Arithmetic with Gates

Adders with Gates

Sequential Logic

Tri-State Buffers

The Verilog Hardware Description Language

Before we start…

No Wait. This is all concurrent!

Verilog Code Structure

Descriptive Modules

Test Bench Modules

Software Tutorial

EDA Tools

Typical Steps in EDA Suites

Quick Overview of EDA Playground

Creating a Playground

Setting up a Playground

Entering Descriptive Code

Entering Test Bench Code

Entering display System Tasks

Simulating with display Tasks

Simulating with EPWave

Simulating with GTKWave

Quick Overview of Modelsim

Download and Installation Tips

Compiling

Simulation Setup

Waveform Simulation

More on Timescales

More Features

Coding Elements of Verilog

Wires and Registers

Number Representation Logic Values

Number Representation Integers

Logic Gates

Higher-Level statements

Data Assignments

Multiplexers and Demultiplexers

Tri-State Buffers in Veriog

Sequential Logic

Blocking vs Nonblocking Assignments

Assignment example in EDA Playground

Blocking Results

Nonblocking Results

Nonintuitive Results

A Combinational System Example

Let’s make a 4-bit Adder!

A Verilog Implementation

Simulating with Multiple Source Files

Simulation

Test Bench

Propagation Delays

An Alternative Implementation in Modelsim

Multiple Bit Signals in Modelsim

A Sequential System Example

Let’s make an UpDown Counter!

A Verilog Implementation

Simulation

Wrap Up

Think of all the things we learned!